The LLM quantisation accuracy trade-off: what four bits actually costs

Four-bit quantisation of an 8B model costs 0.32 average benchmark points; three-bit costs 9.32 points on GSM8K alone. That trade buys GPU memory, and memory is concurrency: Qwen3-32B holds 256 KiB of KV cache per token, so every 4,096-token session costs 1 GiB. This is the arithmetic for plant teams told public cloud is out.

Four bits is cheap. Three bits is not.

The LLM quantisation accuracy trade-off is smaller than most procurement conversations assume, right up to the point where it suddenly is not. Dropping to five or four bits costs almost nothing you can measure. Dropping to three costs you arithmetic. Uygar Kurt's January 2026 evaluation ran thirteen llama.cpp quantisation schemes over Llama-3.1-8B-Instruct against GSM8K, HellaSwag, IFEval, MMLU, TruthfulQA and WikiText-2 perplexity, and the shape of the result in the table below is stable enough to plan against.

Q4_K_M gives up 0.32 average points against the F16 baseline for a file 69% smaller. Q3_K_S gives up 3.98, and the interesting part is where that loss lands: 9.32 points on GSM8K, while HellaSwag moves 0.64. Commonsense multiple choice barely notices three-bit weights. Multi-step arithmetic falls off a cliff.

That asymmetry maps onto workloads directly, and it is the whole basis of the rule we apply. Retrieval, classification, extraction and summarisation are commonsense-shaped tasks, and they tolerate four-bit weights without an argument. Anything that chains arithmetic breaks first, and it breaks quietly, returning a confident wrong number instead of an error. So a model doing arithmetic on production data does not run below five bits, and the eval harness carries at least one arithmetic benchmark built from your own domain before anybody signs off on a quantisation level.

Perplexity on its own will not catch this. Q4_K_M and Q3_K_M sit 0.40 apart on WikiText-2 and 4.25 apart on GSM8K.

One hardware fact narrows the choice before accuracy ever enters it. vLLM documents a 2x reduction in model memory and up to a 1.6x throughput improvement from FP8, but supports FP8 W8A8 only on NVIDIA GPUs with compute capability 8.9 or higher, which means Ada Lovelace and Hopper. The A100 is compute capability 8.0. If the fleet you already own is A100s, FP8 is off the table whatever the accuracy data says, and the route runs through INT8, AWQ or GPTQ instead.

SchemeSize reductionGSM8KMMLUAverageWikiText-2 PPL
F16 baselinenone77.6363.5069.477.32
Q8_046.87%77.4863.4369.417.33
Q5_065.19%79.0863.1869.927.43
Q4_K_M69.41%77.4162.4369.157.56
Q3_K_M75.03%73.1662.0168.077.96
Q3_K_S77.23%68.3159.3165.498.96

What smaller weights actually buy is cache

Smaller weights buy KV cache, and the cache is what decides how many people can use the machine. Qwen3-32B publishes its architecture in config.json on the model card: 64 layers, 64 query heads against 8 key-value heads, head dimension 128, bfloat16. Two tensors, sixty-four layers, eight heads, 128 dimensions, two bytes per value works out to 262,144 bytes of cache for every token in flight. That is 256 KiB per token, or almost exactly 1 GiB for one 4,096-token conversation.

The weights are 65.6 GB at bfloat16. You pay that once, at load time, and then it never changes.

The cache is the opposite. It grows with every concurrent user and every additional token of context, which is why a box that demos beautifully for one engineer collapses when the second shift logs in. Grouped-query attention is the only reason these numbers are survivable at all: Qwen3-32B maps 64 query heads onto 8 key-value heads, so the cache is one eighth of what full multi-head attention would demand. For scale, the PagedAttention paper measured OPT-13B, which predates the technique, at 800 KB per token.

So the question to put to whoever is quoting you a server is not how many parameters it holds. It is how many tokens of cache are left once the weights are loaded.

# Qwen3-32B, values taken from config.json on the model card
layers, kv_heads, head_dim, bytes_per_value = 64, 8, 128, 2

kv_per_token = 2 * layers * kv_heads * head_dim * bytes_per_value
# 262144 bytes = 256 KiB per token

kv_per_session = kv_per_token * 4096
# 1073741824 bytes = 1.0 GiB for one 4k-token session

The same 32B model at five sizing points

The table below puts one model on five hardware configurations, computed from published specifications rather than measured on a bench. vLLM's --gpu-memory-utilization default of 0.92 governs how much of each card the engine may claim for weights, activations, graph capture and cache combined.

Two assumptions are stated rather than buried: 2 GB per card for activations and CUDA graph capture, and a 4,096-token working session costing 1 GiB of cache. Both move under real traffic. Treat the session counts as an order of magnitude, not a service level.

None of this is a benchmark. It is division.

Read the last two rows against each other, because that comparison is the argument of this whole post. Two H100 SXM cards at bfloat16 carry roughly 72 sessions and draw up to 1,400 W. One H100 NVL running FP8 weights carries roughly 48 and draws 350 to 400 W. Quantising bought two thirds of the concurrency at a quarter of the power, and it did it purely by handing the cache the memory the weights had been sitting in.

ConfigurationUsable at 0.92WeightsLeft for KV cache4k sessionsGPU power
1× L40S 48 GB, FP8 weights44.2 GB32.8 GB9.4 GB8350 W
2× L40S 48 GB, bfloat16, TP=288.3 GB65.6 GB18.7 GB17700 W
1× H100 NVL 94 GB, bfloat1686.5 GB65.6 GB18.9 GB17350–400 W
1× H100 NVL 94 GB, FP8 weights86.5 GB32.8 GB51.7 GB48350–400 W
2× H100 SXM 80 GB, bfloat16, TP=2147.2 GB65.6 GB77.6 GB72up to 1,400 W
# One H100 NVL, FP8 weights quantised at load time, 8k context.
# vLLM logs the number of KV cache blocks it allocated at startup —
# that line is the only sizing number on this page that is not an estimate.
vllm serve Qwen/Qwen3-32B \
  --quantization fp8 \
  --tensor-parallel-size 1 \
  --max-model-len 8192 \
  --gpu-memory-utilization 0.92 \
  --kv-cache-dtype auto

The binding constraint is your server room

The binding constraint on all of this is the building, not the benchmark. NVIDIA designs a rack holding four DGX H100 systems for 20.4 kW of peak demand per circuit in its SuperPOD data centre design guide. Uptime Institute's 2025 global survey puts the average modal rack density across its whole sample at almost 9 kW, up from 8.3 kW the year before, and reports that 82% of operators have no rack anywhere in their facility above 30 kW.

One AI node is therefore about two ordinary racks' worth of power, delivered into a single cabinet.

This is where most plant deployments should reconsider the card rather than the model. An H100 SXM is rated up to 700 W configurable. An L40S is 350 W and an H100 NVL is 350 to 400 W, both PCIe dual-slot air-cooled parts that drop into servers your facilities team already knows how to cool. Our position: for a first production private-AI workload on a manufacturing site, the correct default is the 350 W air-cooled card, and the SXM node is a decision you defer until measured demand forces it.

The counter-argument is legitimate. SXM gives you 900 GB/s of NVLink against 600 GB/s on the NVL part, and that gap matters as soon as a model has to be sharded across cards. It matters considerably less than a six-month lead time on a liquid-cooling retrofit that plant engineering has to schedule around a shutdown.

Power and cooling arrive long before the GPUs do. Start that conversation in week one, not after the hardware order.

Retrieval offline is easy. Access control offline is not.

Running retrieval without a cloud is a solved engineering problem: the embedding model shares the same GPUs, the vector store runs on ordinary servers, and no document leaves the site. Access control is where offline deployments actually fail, and they fail in a specific, repeatable way.

The failure mode is post-filtering. A naive pipeline fetches the top 50 chunks by vector similarity and then strips the ones the user is not cleared for. Qdrant's own write-up on filtering states the cost directly: apply a low-cardinality filter after the search, and you often end up discarding a large portion of the results the vector search returned. What a search engineer reads as a throughput problem is, on a permissioned corpus, a correctness problem. The user gets a thin, apparently broken answer, and the pressure to loosen the filter starts the same week.

The position we hold here is unpopular with anyone who likes batch jobs. The permission decision belongs inside the query, evaluated against live directory group membership, never against a nightly copy of an access-control table. A drawing reclassified at 09:00 has to be unreachable at 09:01, and in a plant the documents that get reclassified mid-morning are precisely the ones worth protecting. That costs a directory lookup per query. Pay it.

Three behaviours belong in the manuals you read before building that layer. All three are counterintuitive.

  • Elasticsearch combines document-level security queries across a user's roles with OR. Its documentation is explicit that if one role grants access to an index without document level security and another grants access with it, DLS is not applied and that user sees every document in the index.
  • Relevance scores are computed without the role query. Elastic states that DLS does not affect the global index statistics relevancy scoring uses, and that a restricted user could still learn field names and terms existing only in documents they cannot read.
  • Qdrant uses a filterable vector index that builds additional links between the remaining points, so a permission filter there costs throughput rather than silently costing recall.
{
  "indices": [
    {
      "names": [ "plant-documents" ],
      "privileges": [ "read" ],
      "query": {
        "template": {
          "source": "{ \"terms\": { \"acl_groups\": {{#toJson}}_user.metadata.groups{{/toJson}} }}"
        }
      }
    }
  ]
}

Open weights are not open source, and the difference is a clause

Open weights are not open source, and on Llama the difference carries a number. The Llama Community License withdraws the free grant from any licensee whose products exceeded 700 million monthly active users in the calendar month before the release date, requires a separate licence from Meta in that case, and forbids using Llama outputs to improve other foundation models.

Almost no industrial company crosses 700 million users. Almost every legal department still wants to know why the threshold is in the contract at all.

The clause that actually bites is the second one. If your roadmap includes distilling a small in-house model from the outputs of the one you host, that licence closes the door and Apache 2.0 does not. Qwen3-32B ships under Apache 2.0; Mistral-Small-3.2-24B-Instruct-2506 does too. Neither fact transfers to the rest of the family, and that is the trap: Qwen2.5-3B, same vendor, is published under a qwen-research licence, which you cannot tell from the model name.

Open the LICENSE file on the exact checkpoint you intend to deploy. It is the cheapest four minutes in the project.

Questions engineers ask before the hardware order

Does 4-bit quantisation break the model?

Not measurably on most enterprise work. A January 2026 evaluation of llama.cpp schemes on Llama-3.1-8B-Instruct scored Q4_K_M at 69.15 average against a 69.47 F16 baseline. Three bits is where it changes: Q3_K_S lost 9.32 points on GSM8K while commonsense accuracy barely moved, so arithmetic-heavy tasks degrade first.

Can we run FP8 quantisation on the A100s we already own?

No. vLLM documents FP8 W8A8 support only on NVIDIA GPUs with compute capability 8.9 or higher, meaning Ada Lovelace and Hopper. The A100 is compute capability 8.0, so it falls outside that boundary. On an existing A100 fleet the realistic routes are INT8, AWQ or GPTQ weight-only quantisation instead.

Will our existing server room take an AI node?

Check the circuit before the card. NVIDIA designs a rack of four DGX H100 systems for 20.4 kW of peak demand, while Uptime Institute's 2025 survey puts the average modal rack density across its sample at almost 9 kW and reports 82% of operators with no rack above 30 kW anywhere. Air-cooled 350 W cards usually fit; SXM nodes usually do not.

What does it cost to get a quantisation target we can defend?

Engineering and hardware are separate lines. The fixed-price entry point on the engineering side is €4,900 over two weeks, which produces the memory arithmetic, an eval harness built from your own documents, and a defended quantisation level. GPU purchase, rack power and cooling are quoted by your hardware supplier.

When is running models on our own hardware the wrong answer?

When nothing forces it. If no contract, works council agreement or customer NDA bars a hosted API, self-hosting adds an on-call rotation, a facilities dependency and a model that trails the frontier, in exchange for control you were not required to have. It is also wrong when the building cannot supply the power.

Next step

Bring us your corpus and your power budget

Two weeks, fixed price: memory arithmetic against your actual documents and concurrency, a quantisation target defended with an eval harness built from your own domain, and an access-control design your directory can enforce. You keep the numbers whether or not you continue with us.